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| SY89202U Precision 1:8 LVPECL Fanout Buffer with Three /1//2//4 Clock Divider Output Banks General Description The SY89202U is a precision, high-speed, integrated clock divider LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output banks are phase matched and can be configured for pass-through (/1), /2 or /4 divide ratios. The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any AC- or DC-coupled signal as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The low skew, low jitter outputs are 800mV, 100k compatible LVPECL, with extremely fast rise/fall times guaranteed to be less than 220ps. The EN (enable) input guarantees that the /1, /2 and /4 outputs will start from the same state without any runt pulse after an asynchronous MR (master reset) is asserted. This is accomplished by enabling the outputs after a four-clock delay to allow the counters to synchronize. (R) The SY89202U is part of Micrel's Precision Edge product family. All support documentation can be found at Micrel's web site at: www.micrel.com Precision Edge (R) Features * Three low-skew LVPECL output banks with programmable /1, /2 and /4 divider options * Three independently programmable output banks * Guaranteed AC performance over temp and voltage: - >1.5GHz clock frequency (fMAX) - <930ps In-to-Out tpd - <220ps tr/tf * Ultra-low jitter design: - <1psRMS random jitter (RJ) - <10psPP total jitter (clock) * Internal input termination * Patent-pending input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS) * 800mV LVPECL output swing * CMOS/TTL-compatible output enable (EN) and divider select control * Power supply 2.5V +5% or 3.3V +10% o o * -40 C to +85 C industrial temperature range (R) * Available in 32-pin MLF package Applications * All SONET/SDH channel select applications * All Fibre Channel multi-channel select applications * All Gigabit Ethernet multi-channel select Applications Markets * * * * LAN/WAN Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology. June 2006 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U Functional Block Diagram June 2006 2 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U Ordering Information (1) Part Number SY89202UMG SY89202UMGTR Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals Only. 2. Tape and Reel. (2) Package Type MLF-32 MLF-32 Operating Range Industrial Industrial Package Marking SY89202U with Pb-Free bar-line indicator SY89202U with Pb-Free bar-line indicator Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free Pin Configuration 32-Pin MLF (MLF-32) (R) June 2006 3 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U Pin Description Pin Number 2, 7, 8 Pin Name DIVSEL1 DIVSEL2 DIVSEL3 Pin Function Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the three banks of outputs. Note that each of these inputs is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The inputswitching threshold is VCC/2. Differential Input: This input pair is the differential signal input to the device. This input accepts AC- or DC-coupled signals as small as 100mV. The input pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. Reference Voltage: This output biases to VCC -1.2V. It is used for AC-coupling inputs IN and /IN. For AC-coupled applications, connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. Single-Ended Input: This TTL/CMOS input disables and enables the Q0 - Q7 outputs. This input is internally connected to a 25kW pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. For the input enable and disable functional description, refer to "Timing Diagram" section. Positive power supply. Bypass with 0.1uF//0.01uF low ESR capacitors as close to VCC pins as possible. Bank 2 LVPECL differential output pairs controlled by DIVSEL2: LOW, Q4 - Q6 = /2, HIGH, Q4 - Q6 = /4. Unused output pairs may be left open. Each output is designed to drive 800mV into 50 terminated at VCC-2V. Bank 1 LVPECL differential output pairs controlled by DIVSEL1: LOW, Q0 - Q3 = /1, HIGH, Q0 - Q3 = /2. Unused output pairs may be left open. Each output is designed to drive 800mV into 50 terminated at VCC-2V. Bank 3 LVPECL differential output pair controlled by DIVSEL3: LOW, Q7 = /2, HIGH, Q7 = /4. Unused output pairs may be left open. Each output is designed to drive 800mV into 50W terminated at VCC-2V. Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously sets Q0 - Q7 outputs LOW and /Q0 - /Q7 outputs HIGH, and holds them in that state as long as the /MR input remains LOW. This input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The input-switching threshold is VCC/2. Ground: Ground pin and exposed pad must be connected to the same ground plane. 3, 6 IN, /IN 4 VT 5 VREF-AC 9 EN 10, 19, 22, 31 16, 15, 14, 13, 12, 11 30, 29, 28, 27, 26, 25, 24, 23 18, 17 VCC Q4, /Q4, Q5, /Q5, Q6, /Q6 Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3 Q7, /Q7 32 /MR 1, 20, 21 GND, Exposed Pad Truth Table /MR 0 1 1 1 Notes: 1. 2. 3. /MR asynchronously forces Q0 - Q7 LOW (/Q0 - /Q7 HIGH). EN forces Q0 - Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to "Timing Diagram" section. EN synchronously enables the outputs between 2 and 6 input clock cycles after the rising edge of EN. Refer to "Timing Diagram" section. ( 1) EN ( 2, 3) DIVSEL1 X X 0 1 DIVSEL2 X X 0 1 DIVSEL3 X X 0 1 Q0 - Q3 0 0 /1 /2 Q4 - Q6 0 0 /2 /4 Q7 0 0 /2 /4 X 0 1 1 June 2006 4 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U Absolute Maximum Ratings(1) Supply Voltage (VCC) .............................-0.5V to +4.0V Input Voltage (VIN) .....................................-0.5V to VCC Termination Current Source or sink current on VT .................... 100mA Output Current Source or sink current on IN, /IN................ 50mA VREF-AC Current Source or sink current on VREF-AC .............. 1.5mA Lead Temperature (soldering, 20 sec.)............ +260C Storage Temperature (Ts) ...................-65C to 150C Operating Ratings(2) Supply Voltage (VCC) ....................+2.375V to +2.625V ........................................................ +3.0V to +3.6V Ambient Temperature (TA) .................. -40C to +85C (4) Package Thermal Resistance (R) MLF (JA) Still-Air ........................................................ 35C/W (R) MLF (JB) Junction-to-Board ...................................... 20C/W DC Electrical Characteristics(5) TA = -40C to +85C, unless otherwise stated. Symbol VCC ICC RDIFF_IN RIN VIH VIL VIN VDIFF_IN VREF-AC IN-to-VT Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameter Power Supply Power Supply Current Differential Input Resistance (IN-to-/IN) Input Resistance (IN-to-VT) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| Output Reference Voltage (VREF-AC) Voltage from Input to VT Condition Min 2.375 3.0 Typ Max 2.625 3.6 Units V V mA V V mV mV No load, max. VCC 90 45 1.2 0 See Figure 1a. See Figure 1b. 100 200 VCC-1.3 125 100 50 180 110 55 VCC VIH-0.1 VCC VCC-1.2 VCC-1.1 1.8 V V June 2006 5 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U LVPECL Outputs DC Electrical Characteristics(6) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C; RL = 50 to VCC-2V, unless otherwise stated. Symbol VOH VOL VOUT VDIFF-OUT Parameter Output HIGH Voltage Q, /Q Output LOW Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing |Q - /Q| See Figure 1a. See Figure 1b. Condition Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC -1.695 Units V V mV mV LVTTL/CMOS DC Electrical Characteristics(6) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, unless otherwise stated. Symbol VIH VIH IIH IIL Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min 2.0 Typ Max 0.8 Units V V A A -125 -300 30 June 2006 6 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U AC Electrical Characteristics(7) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated. Symbol fMAX tpd tpd Tempco Parameter Maximum Output Toggle Frequency Maximum Input Frequency Differential Propagation Delay /MR - Q Propagation Delay Differential Propagation Delay Temperature Coefficient Within-bank Skew tskew Bank-to-Bank Skew Bank-to-Bank Skew Part-to-Part Skew Deterministic Jitter (DJ) tJitter Random Jitter (RJ) Total Jitter Cycle-to-Cycle Jitter tr, tf Notes: 7. 8. 9. Measured with 100mV input swing. See "Timing Diagrams" section for definition of parameters. High-frequency AC-parameters are guaranteed by design and characterization. Within-bank skew is the difference in propagation delays among the outputs within the same bank. Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset between each bank, after MR is applied. Condition Output swing 400mV IN-to-Q Min 1.5 3.0 530 Typ Max Units GHz GHz 700 930 900 ps ps fs/oC 115 Within same fanout bank, Note 8 Same divide setting, Note 9 Different divide setting, Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 20% to 80%, At full output swing. 70 130 10 15 25 25 35 50 200 10 1 10 1 220 ps ps ps ps psPP psRMS psPP psRMS ps Output Rise/Fall Time 10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 11. Deterministic jitter is measured with a K28.7 101010 pattern, measured at 7 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagrams 1 2 3 4 IN, /IN /MR V /2 CC /MR asynchronously resets the outputs. EN tpd EN = HIGH /1 Output /2 Output /4 Output Outputs go HIGH simultaneously after 4 complete input clock (IN) periods after /MR is de-asserted. Timing Diagram Showing Reset with Output Enabled June 2006 8 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U 1 2 3 4 IN, /IN EN VCC /2 Enable asserted External /1 Output External /2 Output External /4 Output Outputs go HIGH simultaneously after EN is asserted. The number of IN clock cycles after EN is asserted before the outputs go HIGH varies from 2 to 6 cycles (4 cycles shown). Timing Diagram Showing Enable Timing 1 2 3 4 IN, /IN Enable de-asserted to disable Q0 - Q7 Outputs EN VCC /2 /1 Output /2 Output /4 Output Outputs go low in sequence after EN is de-asserted. The /4, /2 , /1 outputs go LOW in that order. The number of IN clock cycles after EN is de-asserted varies from 2 to 6 cycles (4 cycles shown). Timing Diagram Showing Disable Timing June 2006 9 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U Typical Operating Characteristics Functional Characteristics June 2006 10 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U Input and Output Stages Figure 2a. Simplified Differential Input Stage Figure 2b. Simplified LVPECL Output Stage Input Interface Applications Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface (DC-Coupled) Figure 3f. LVDS Interface (AC-Coupled) June 2006 11 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U LVPECL Output Interface Applications LVPECL has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50- and 100-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel Termination-Thevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced. Figure 4. Parallel Termination-Thevenin Equivalent Figure 5. Parallel Termination (3-Resistor) Related Product and Support Documentation Part Number SY89200U HBW Solutions Function Ultra-precision 1:8 LVDS Fanout with Three /1//2//4 Clock Divider Output Banks New Products and Applications MLF Application Note (R) Data Sheet Link http://www.micrel.com:8000/iphrase/query?query=*SY892 02U* http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf June 2006 12 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89202U 32-Pin MicroLeadFrame(R) (MLF-32) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. June 2006 13 M9999-061206-B hbwhelp@micrel.com or (408) 955-1690 |
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